DS90LV110ATMT

TSSOP-28, data/clock distributor, failsafe, Low jitter, 400 Mbps, +3.3 V, 320mV

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Price:: US $3.23~3.38 / piece [Get Latest Price]

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	US $3.23~3.38

PartNumber:: DS90LV110ATMT

Brand:: National Semiconductor - NS | Pack: TSSOP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-12

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Part Number:DS90LV110ATMT
US $3.23 - 3.38
HCPL-7800A

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STK795-810

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Product Summary

The DS90LV110ATMT is a 1 to 10 LVDS data/clock distributor with failsafe. The DS90LV110ATMT is a 1 to 10 data/clock distributor utilizing LVDS(Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. The DS90LV110ATMT can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz.

Parametrics

DS90LV110ATMT absolute maximum ratings: (1)Supply Voltage (VDD-VSS): -0.3V to +4V; (2)LVCMOS/LVTTL Input Voltage(EN): -0.3V to (VCC + 0.3V); (3)LVDS Receiver Input Voltage(IN+, IN.): -0.3V to +4V; (4)LVDS Driver Output Voltage(OUT+, OUT.): -0.3V to +4V; (5)Junction Temperature: +150℃; (6)Storage Temperature Range: -65℃ to +150℃; (7)Lead Temperature(Soldering, 4 sec.): +260℃; (8)Maximum Package Power Dissipation at 25℃: 28L TSSOP 2.115 W.

Features

DS90LV110ATMT fatures: (1)Low jitter 400 Mbps fully differential data path; (2)145 ps (typ) of pk-pk jitter with PRBS = 223.1 data pattern at 400 Mbps; (3)Single +3.3 V Supply; (4)Balanced output impedance; (5)Output channel-to-channel skew is 35ps (typ); (6)Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.; (7)LVDS receiver inputs accept LVPECL signals; (8)LVDS input failsafe; (9)Fast propagation delay of 2.8 ns (typ); (10)Receiver open, shorted, and terminated input failsafe; (11)28 lead TSSOP package; (12)Conforms to ANSI/TIA/EIA-644 LVDS standard.