CY7C1518KV18-333BZC

Product Summary

The CY7C1518KV18-333BZC is a 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The CY7C1518KV18-333BZC consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from the CY7C1518KV18-333BZC in the system design.

Parametrics

CY7C1518KV18-333BZC absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied:–55℃ to +125℃; (3)Supply Voltage on VDD Relative to GND:–0.5V to +2.9V; (4)Supply Voltage on VDDQ Relative to GND:–0.5V to +VDD; (5)DC Applied to Outputs in High-Z:–0.5V to VDDQ + 0.3V; (6)DC Input Voltage:–0.5V to VDD + 0.3V; (7)Current into Outputs (LOW):20 mA; (8)Static Discharge Voltage (MIL-STD-883, M. 3015): > 2001V; (9)Latch-up Current:> 200 mA.

Features

CY7C1518KV18-333BZC features: (1)72-Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36); (2)333 MHz Clock for High Bandwidth; (3)2-word Burst for reducing Address Bus Frequency ; (4)Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz ; (5)Two Input Clocks (K and K) for precise DDR Timing: SRAM uses rising edges only; (6)Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches; (7)Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems; (8)Synchronous Internally Self-timed Writes; (9)DDR-II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH; (10)Operates similar to DDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW; (11)1.8V Core Power Supply with HSTL Inputs and Outputs; (12)Variable Drive HSTL Output Buffers; (13)Expanded HSTL Output Voltage (1.4V–VDD): Supports both 1.5V and 1.8V IO supply; (14)Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm); (15)Offered in both Pb-free and non Pb-free Packages; (16)JTAG 1149.1 compatible Test Access Port; (17)Phase Locked Loop (PLL) for Accurate Data Placement.

Diagrams